The present technology relates to a storage control device. More specifically, the present technology relates to a storage control device, a storage device, and an information processing system for a memory, as well as to a processing method in such devices and system.
In an information processing system, a DRAM (Dynamic Random Access Memory) and the like are used as a work memory. Such a DRAM is typically a volatile memory, and storage contents thereof disappear once power supply is stopped. Meanwhile, in recent years, a non-volatile memory (NVM) has become widely used. Such a non-volatile memory falls into the general classification of a flash memory corresponding to a data access in the unit of a large size and a non-volatile random access memory (NVRAM) that enables a high-speed random access in the unit of a small size. Here, a typical example of the flash memory may include a NAND-type flash memory. On the other hand, examples of the non-volatile random access memory may include a ReRAM (Resistance RAM), a PCRAM (Phase-Change RAM), an MRAM (Magnetoresistive RAM), and the like.
In a processing of data write to a memory cell, a non-volatile memory assumes a writing step that writes data to a memory cell and a verifying step that reads data from the memory cell and performs verification by comparing the read data with the write data. At the time of write to the memory cell, these steps are repeated until data matching is confirmed from a result of comparison of data in the verifying step following the writing step. Since the memory cell has a certain range of variation in the characteristics, and the similar variation is also found in the number of these steps, a busy time arising during a write operation does not become a fixed period of time. Accordingly, for a write busy time of the non-volatile memory, a typical value and a maximum value are specified as a general rule. The typical value is determined by the average frequency of success in verification during a write operation, while the maximum value is determined by the maximum frequency of repetition of the writing step and the verifying step. If these steps are repeated up to the maximum number of times, a memory cell that fails in the verification may be often judged to be a defective cell.
Due to such a variation in the writing time, the write performance of the non-volatile memory is deteriorated by a cell with a long writing time. Typically in the non-volatile memory, a write operation is carried out to a write unit often referred to as a page that is configured of a plurality of memory cells concurrently. Consequently, even if only a few memory cells in the page have a long writing time due to the above-described variation, it is difficult to start a write to the next page until a write to such memory cells is completed, resulting in deterioration in the overall write processing performance. The same is true for a non-volatile memory employing a multi-bank configuration that has a plurality of non-volatile memory banks using a page as a writing unit. A page writing time of a certain bank is increased due to a variation, and thereby any other banks that have already completed a write operation are put in a state of waiting for a start of write to the next page until such a bank completes its write operation, resulting in deterioration in the write performance of the overall non-volatile memory. More specifically, in either case, although a page of a bank that has already completed a write operation is put in a state capable of starting a write operation if only it receives the next data, the next data entry remains in a standby state until all the banks complete write operation thereof, causing the write performance to degrade.
On the contrary, a method has been proposed that prevents a data transfer time from being an overhead on a start of the next write operation by transferring the next write data to a buffer internal to a non-volatile memory during write busy time (for example, see Japanese Unexamined Patent Application Publication No. 2003-196989). Further, also for a multi-bank configuration, a method has been proposed that reduces an overhead on a start of write operation by providing a buffer for each bank (for example, see Japanese Unexamined Patent Application Publication No. 2007-080475).